Automatic Device Design Optimization with TCAD Frameworks

A design optimization method is presented which utilizes automatic optimization capabilities within TCAD frameworks. This method is applied to doping profile optimizations of ultra-low-power CMOS transistors with 0.25 and 0.1 μm gate lengths. Two different performance goals are utilized, to maximize the drive current of an NMOS transistor and to minimize the gate delay time of a CMOS inverter stage. These optimizations result in an asymmetric doping profile with a channel peak near the source. Gaussian functions are used to simplify the doping structure without much of a performance loss. The inverter speed of the 0.1 μm technology is improved by almost 1003 compared to an inverter with uniformly doped devices delivering the same offstate leakage current.